Second International Workshop on Formal Methods for

Globally Asynchronous Locally Synchronous Design (FMGALS'2005)
In cooperation with ACM SIGDA and SIGARCH

  Colocated with ACM-IEEE MEMOCODE'2005 -- July 15, 2005 -- Verona, Italy

Invited Keynote Speakers
Ad Peeters, Philips Research
Alberto Sangiovanni Vincentelli, UC Berkeley

General cochairs
Sandeep Shukla, Virginia Tech
Ken Stevens, Intel

Program cochairs
Montek Singh, UNC Chapel Hill
Jean-Pierre Talpin,

Local Arrangement Chair
Franco Fummi, Verona
Program committee
Supratik Chakraborty, IITB
Benoit Caillaud, INRIA
Luca Carloni, Columbia
Doug Edwards, Manchester
Mark Greenstreet, British Columbia
Rajesh Gupta, UC San Diego

Soha Hassoun, Tufts University
Luciano Lavagno, Poly Torino

Diana Marculescu, CMU
Paul Le Guernic, INRIA
Chris Myers, Utah
Sandeep Shukla, Virginia Tech
R. K. Shyamasundar, TIFR
Montek Singh, UNC Chapel Hill

Ken Stevens, Intel
Jean-Pierre Talpin, INRIA               
Mickael Theobald, CMU
Georgios Theodoropoulos, Birmingham
Alex Yakovlev, Newcastle


FMGALS'2003, Pisa


July is a highly touristic season in Verona. Prospective participants are invited to book  reserved hotel accommodation lots by May 15th.
CALL FOR PAPERS  As chips grow in speed and complexity, global control of an entire chip using a single clock is becoming increasingly challenging. In the future, multi-core and large-scale systems on chip (SoC) designs are therefore likely to be composed of several timing domains. Global Asynchrony and Local Synchrony (GALS)  is emerging as the paradigm of choice for SOC design with multiple timing domains. In GALS systems, each timing domain is locally clocked, and asynchronous communication schemes are used to glue all of the domains together.  Thus, unlike purely asynchronous design, GALS design is able to make use of the significant industrial investment in synchronous design tools.

There is an urgent need for formal methods for GALS systems.  In synchronous designs, formal methods and design automation have played an enabling role in the continuing quest for chips with ever greater complexity.  Due to the inherent subtleties of asynchronous circuit design, formal methods are likely to be vital to the success of the GALS paradigm.  This workshop aims at bringing together researchers from different communities interested in GALS design, and in applying formal methods in creating CAD tools enabling correct by construction GALS design.

FMGALS'2005 invites papers on formal methods for GALS systems or that target any type of architecture combining synchronous and asynchronous notions of timing.  Submissions reporting preliminary work are also encouraged.  In particular, contributions are invited on the following topics, but not limited to:

- formal design and synthesis techniques for GALS systems
- design and architectural transformations and equivalences
- formal verification of GALS systems
- formal methods for analysis of GALS systems
- hardware compilation of GALS system
- latency-insensitive synchronous systems
- mixed synchronous-asynchronous systems
- synchronous/asynchronous interaction at different levels
- clocking, interconnect and interface issues in deep-submicron design
- modeling of interfaces between multiple timing domains
- system decomposition into GALS architectures
- formal aspects of system-on-chip (SoC and NoC) design
- motivating case studies, comparisons, and applications.

Proceedings of the FMGALS workshop will be published with Elsevier in the Electronic Notes on Theoretical Computer Science series (ENTCS).

Submissions should be sent by e-mail to both program cochairs (Montek at and Talpin at and be prepared with LaTeX using the
ENTCS style. Key dates are:

Abstract submission deadline:            April 3, 2005
Final submission deadline:                 April 10, 2005
Notification sent to authors:               May 1, 2005
Final version due:                             May 15, 2005