PRELIMINARY PROGRAM

9:00 - Keynotes - Chair: Rajesh Gupta

Tag Systems: a Formal Model for Heterogeneous System Analysis and Design
Alberto Sangiovanni Vicentelli, University of California at Berkeley

10:00 - Break

10:30 - Session I - Chair: Sandeep Shukla

10:30 - Design challenges for a differential power analysis ware GALS based AES crypto-ASIC
              Frank Gurkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolgang Fichtner.

10:55 - A verification approach for GALS integration of synchronous components.
             Frederic Doucet,  Massimiliano Menarini, Ingolf H. Kruger, Jean-Pierre Talpin, Rajesh Gupta.

11:20 - Another glance at relay stations in latency-insensitive design.
             Julien Boucaron, Jean-Vivien Millo, Robert de Simone.

11:45 - A functional programming framework for latency insensitive protocol validation.
             Syed Suhaib, Deepak Mathaikutty, Sandeep Shukla, David Berner, Jean-Pierre Talpin.

12:00 - Lunch

14:00 - Session II - Chair: Ken Stevens

14:00 - The role of back-pressure in implementing latency-insensitive systems.
              Luca Carloni.

14:25 - Opportunities and challenges in process-algebraic verification of asynchronous circuit designs.
              Xu Wang, Marta Kwiatkowska and G. Theodoropoulos.

14:40 - Break

15:10 - Session III - Chair: Jean-Pierre Talpin

15:10 - Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis.
             Ankur Agiwal and Montek Singh.
 
15:35 - GALS Test Chip on 130nm Process.
              David Bormann.

16:00 - From weakly endochronous systems to delay-insensitive circuits.
             Sohini Dasgupta, Dumitru Potop-Butucaru, Benoit Caillaud, Alexandre Yakovlev.

16:25 - A survey of desynchronization in a polychronous model of computation.
             Julien Ouy.

16:40 - Panel - Chair: Montek Singh

18:00 - End of the workshop