Results of the
2nd MEMOCODE Codesign Contest

• Teams
• Submitted Designs
• Results
• Overall Ranking and Awards
• Judges and Award Sponsors

Of the 27 teams that requested access to the reference implementation of the Cryptosorter design, 8 teams provided a solution before the contest deadline on 9 March. The table below lists the affiliation and configuration of each team. The teams are listed in contest-enrollment order.

Notes:

• The teams are listed in enrollment order
• Teams are identified as team name, where name is the first name of one of the team members (usually the contact with memocontest08@gmail.com).

Several teams agreed to share their solutions to the contest assignment. The table below lists the submission and the corresponding documentation.

By downloading these design files, you agree to have read and understood the following disclaimer.

THESE DESIGN FILES ARE PROVIDED BY THE AUTHORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The following table lists, for each team, the overall speedup, the platform used, and the design languages used. The overall speedup is defined by the geometric mean of the set of testbench configurations. The speedup is further normalized according to the platform calibration rules. The table rows are sorted according to the overall speedup.

Notes:

• Under Design languages, HDL means either VHDL or Verilog.
• Under Platform, XUP is the Xilinx XUP board. The XC2VP100 Amirix board is the only non-XUP entry. Based on the calibration rules, the use of this FPGA incurs a normalization factor of 3.2 due to its higher capacity.
• Team sunita submitted two designs which different design flows. The table includes both of their submissions.

Besides the evaluation based on performance, the judging panel also evaluated the elegance of each design. Elegance is a subjective appreciation, and it considers factors such as cleverness of the algorithm, exploitation of parallelism, quality and clarity of the design documentation, and quality and clarity of the source code. Each of the submissions was ranked by each of the 5 judges according to this subjective appreciation. The individual rankings were then combined, by majority voting, into a top-5 of elegant designs.

This contest includes awards in three categories: Most Efficient Design, Highest Performance Design, Best Figures of Merit Using a High Level Language.

Based on absolute performance, and a top-ranking in elegance, team kermin becomes winner in the Highest Performance Design category. The same design would also be entitled to the Most Efficient Design since all teams (apart from team eric) used the same platform. However, the contest rules allow a team to win in only a single category of Most Efficient Design and Highest Performance Design. The judging panel therefore concluded to award an honorable mention to team vijay, based on the consensus that this design has superior elegance.

For the special Xilinx award in the category Best Figures of Merit Using a High Level Language there were essentially two entries: team kermin and team sunita (2). Xilinx is impressed with the result of team brian. Team brian achieved the best system result, while only using a solution programmed in C on the processor. The winner of the special Xilinx award is team kermin. Xilinx is delighted to see that the best performance in the given time has been reached with a high-level language input.

• Krste Asanovic, UC Berkeley
• Satrajit Chatterjee, Intel
• James C. Hoe, Carnegie Mellon University
• Patrick Schaumont, Virginia Tech
• Kees Vissers, Xilinx Research Labs

Awards are sponsored by the following companies and organizations