Overview |
Generated on |
Thu May 05 13:36:20 2005 |
Source |
F:/fpga/proj/DesignContest08_vjs_64bit_blk4/system.xmp |
EDK Version |
7.1.2 |
FPGA Family |
virtex2p |
Device |
xc2vp30ff896-7 |
# IP Instantiated |
18 |
# Processors |
2 |
# Busses |
3 |
|
SYSTEM PINOUT |
These are the system ports listed in the MHS file.
|
ATTRS Key CLK are clock ports INTR are interrupt ports BUF or REG are ports that instantiate or infer IOB primitives:
|
NAME |
DIR |
[MSB:LSB] |
SIG |
ATTRS |
fpga_0_DDR_CLK_FB |
I |
1 |
ddr_feedback_s |
|
fpga_0_RS232_Uart_1_RX_pin |
I |
1 |
fpga_0_RS232_Uart_1_RX |
|
sys_clk_pin |
I |
1 |
dcm_clk_s |
|
sys_rst_pin |
I |
1 |
sys_rst_s |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin |
IO |
7:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin |
IO |
63:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin |
O |
12:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin |
O |
1:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn |
|
|
|
NAME |
DIR |
[MSB:LSB] |
SIG |
ATTRS |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin |
O |
1:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin |
O |
1:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin |
O |
2:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin |
O |
2:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin |
O |
7:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn |
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn |
|
fpga_0_DDR_CLK_FB_OUT |
O |
1 |
ddr_clk_feedback_out_s |
|
fpga_0_RS232_Uart_1_TX_pin |
O |
1 |
fpga_0_RS232_Uart_1_TX |
|
|
|
ppc405_0
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
PLBCLK |
I |
1 |
sys_clk_s |
2 |
RSTC405RESETCHIP |
I |
1 |
RSTC405RESETCHIP |
3 |
RSTC405RESETCORE |
I |
1 |
RSTC405RESETCORE |
4 |
RSTC405RESETSYS |
I |
1 |
RSTC405RESETSYS |
5 |
BRAMISOCMCLK |
I |
1 |
sys_clk_s |
6 |
CPMC405CLOCK |
I |
1 |
proc_clk_s |
7 |
C405RSTCHIPRESETREQ |
O |
1 |
C405RSTCHIPRESETREQ |
8 |
C405RSTCORERESETREQ |
O |
1 |
C405RSTCORERESETREQ |
9 |
C405RSTSYSRESETREQ |
O |
1 |
C405RSTSYSRESETREQ |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
MASTER |
ISOCM |
ISOCM |
iocm |
iocm_cntlr |
MASTER |
IPLB |
PLB |
plb |
NA |
MASTER |
DPLB |
PLB |
plb |
NA |
TRANSPARENT |
JTAGPPC |
NA |
jtagppc_0_0 |
jtagppc_0 |
|
General |
IP Core |
ppc405 |
Version |
2.00.c |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_DCR_RESYNC |
0 |
C_DETERMINISTIC_MULT |
0 |
C_DISABLE_OPERAND_FORWARDING |
1 |
C_DSOCM_DCR_BASEADDR |
0b0000100000 |
C_DSOCM_DCR_HIGHADDR |
0b0000100011 |
C_ISOCM_DCR_BASEADDR |
0b0000010000 |
C_ISOCM_DCR_HIGHADDR |
0b0000010011 |
C_MMU_ENABLE |
1 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
855 |
556 |
153 |
PPC405s |
1 |
2 |
50 |
|
|
ppc405_1
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
TRANSPARENT |
JTAGPPC |
NA |
jtagppc_0_1 |
jtagppc_0 |
|
General |
IP Core |
ppc405 |
Version |
2.00.c |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_DCR_RESYNC |
0 |
C_DETERMINISTIC_MULT |
0 |
C_DISABLE_OPERAND_FORWARDING |
1 |
C_DSOCM_DCR_BASEADDR |
0b0000100000 |
C_DSOCM_DCR_HIGHADDR |
0b0000100011 |
C_ISOCM_DCR_BASEADDR |
0b0000010000 |
C_ISOCM_DCR_HIGHADDR |
0b0000010011 |
C_MMU_ENABLE |
1 |
MEMORY MAP
|
D=DATA ADDRESSABLE I=INSTRUCTION ADDRESSABLE |
D |
I |
BASE |
HIGH |
MODULE |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
855 |
556 |
153 |
PPC405s |
1 |
2 |
50 |
|
|
|
iocm
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
ISOCM_Clk |
I |
1 |
sys_clk_s |
2 |
sys_rst |
I |
1 |
sys_bus_reset |
Bus Connections |
TYPE |
NAME |
BIF |
MASTER |
ppc405_0 |
ISOCM |
SLAVE |
iocm_cntlr |
ISOCM |
|
General |
IP Core |
isocm_v10 |
Version |
2.00.a |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_ISARCVALUE |
0xFF |
C_ISCNTLVALUE |
0x85 |
C_NUM_MASTERS |
1 |
C_NUM_SLAVES |
1 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
373 |
556 |
67 |
|
|
opb
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
SYS_Rst |
I |
1 |
sys_bus_reset |
2 |
OPB_Clk |
I |
1 |
sys_clk_s |
Bus Connections |
TYPE |
NAME |
BIF |
MASTER |
plb2opb |
MOPB |
SLAVE |
RS232_Uart_1 |
SOPB |
|
General |
IP Core |
opb_v20 |
Version |
1.10.c |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0xFFFFFFFF |
C_DEV_BLK_ID |
0 |
C_DEV_MIR_ENABLE |
0 |
C_DYNAM_PRIORITY |
0 |
C_EXT_RESET_HIGH |
1 |
C_HIGHADDR |
0x00000000 |
C_NUM_MASTERS |
1 |
|
|
Name |
Value |
C_NUM_SLAVES |
1 |
C_OPB_AWIDTH |
32 |
C_OPB_DWIDTH |
32 |
C_PARK |
0 |
C_PROC_INTRFCE |
0 |
C_REG_GRANTS |
1 |
C_USE_LUT_OR |
1 |
|
|
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
24 |
13696 |
0 |
Slice Flip Flops |
6 |
27392 |
0 |
4 input LUTs |
41 |
27392 |
0 |
bonded IOBs |
278 |
556 |
50 |
|
|
plb
|
 |
|
General |
IP Core |
plb_v34 |
Version |
1.02.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0b1111111111 |
C_DCR_AWIDTH |
10 |
C_DCR_DWIDTH |
32 |
C_DCR_INTFCE |
0 |
C_EXT_RESET_HIGH |
1 |
C_HIGHADDR |
0b0000000000 |
C_IRQ_ACTIVE |
1 |
|
|
Name |
Value |
C_NUM_OPBCLK_PLB2OPB_REARB |
5 |
C_PLB_AWIDTH |
32 |
C_PLB_DWIDTH |
64 |
C_PLB_MID_WIDTH |
1 |
C_PLB_NUM_MASTERS |
2 |
C_PLB_NUM_SLAVES |
3 |
|
|
|
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
251 |
13696 |
1 |
Slice Flip Flops |
68 |
27392 |
0 |
4 input LUTs |
421 |
27392 |
1 |
bonded IOBs |
955 |
556 |
171 |
|
|
|
plb2opb
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
PLB_Clk |
I |
1 |
sys_clk_s |
2 |
OPB_Clk |
I |
1 |
sys_clk_s |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
MASTER |
MOPB |
OPB |
opb |
NA |
SLAVE |
SPLB |
PLB |
plb |
NA |
|
General |
IP Core |
plb2opb_bridge |
Version |
1.01.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BGI_TRANSABORT_CNT |
31 |
C_CLK_ASYNC |
1 |
C_DCR_AWIDTH |
10 |
C_DCR_BASEADDR |
0b1111111111 |
C_DCR_DWIDTH |
32 |
C_DCR_HIGHADDR |
0b0000000000 |
C_DCR_INTFCE |
0 |
C_FAMILY |
virtex2p |
C_HIGH_SPEED |
1 |
C_INCLUDE_BGI_TRANSABORT |
1 |
C_IRQ_ACTIVE |
1 |
C_NO_PLB_BURST |
0 |
C_NUM_ADDR_RNG |
1 |
C_OPB_AWIDTH |
32 |
|
|
Name |
Value |
C_OPB_DWIDTH |
32 |
C_PLB_AWIDTH |
32 |
C_PLB_DWIDTH |
64 |
C_PLB_MID_WIDTH |
1 |
C_PLB_NUM_MASTERS |
2 |
C_RNG0_BASEADDR |
0x40600000 |
C_RNG0_HIGHADDR |
0x4060ffff |
C_RNG1_BASEADDR |
0xFFFFFFFF |
C_RNG1_HIGHADDR |
0x00000000 |
C_RNG2_BASEADDR |
0xFFFFFFFF |
C_RNG2_HIGHADDR |
0x00000000 |
C_RNG3_BASEADDR |
0xFFFFFFFF |
C_RNG3_HIGHADDR |
0x00000000 |
|
|
|
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
644 |
13696 |
4 |
Slice Flip Flops |
555 |
27392 |
2 |
4 input LUTs |
510 |
27392 |
1 |
bonded IOBs |
404 |
556 |
72 |
|
|
|
isocm_bram
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
TRANSPARENT |
PORTA |
NA |
isocm_porta |
iocm_cntlr |
TRANSPARENT |
PORTB |
NA |
isocm_portb |
iocm_cntlr |
|
General |
IP Core |
bram_block |
Version |
1.00.a |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_FAMILY |
virtex2p |
C_MEMSIZE |
4096 |
C_NUM_WE |
2 |
C_PORT_AWIDTH |
32 |
C_PORT_DWIDTH |
64 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
330 |
556 |
59 |
BRAMs |
2 |
136 |
1 |
|
|
|
DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
PLB_Clk |
I |
1 |
sys_clk_s |
2 |
Clk90_in |
I |
1 |
clk_90_s |
3 |
Clk90_in_n |
I |
1 |
clk_90_n_s |
4 |
PLB_Clk_n |
I |
1 |
sys_clk_n_s |
5 |
DDR_Clk90_in |
I |
1 |
ddr_clk_90_s |
6 |
DDR_Clk90_in_n |
I |
1 |
ddr_clk_90_n_s |
7 |
DDR_DQS |
IO |
7:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS |
8 |
DDR_DQ |
IO |
63:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ |
9 |
DDR_Addr |
O |
12:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr |
10 |
DDR_BankAddr |
O |
1:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr |
11 |
DDR_CASn |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn |
12 |
DDR_CKE |
O |
1:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE |
13 |
DDR_CSn |
O |
1:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn |
14 |
DDR_RASn |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn |
15 |
DDR_WEn |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn |
16 |
DDR_DM |
O |
7:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM |
17 |
DDR_Clk |
O |
3:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s |
18 |
DDR_Clkn |
O |
3:0 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0 |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
SLAVE |
SPLB |
PLB |
plb |
NA |
|
General |
IP Core |
plb_ddr |
Version |
1.11.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_DDR_AWIDTH |
13 |
C_DDR_BANK_AWIDTH |
2 |
C_DDR_CAS_LAT |
2 |
C_DDR_COL_AWIDTH |
10 |
C_DDR_DWIDTH |
64 |
C_DDR_TMRD |
20000 |
C_DDR_TRAS |
60000 |
C_DDR_TRC |
90000 |
C_DDR_TRCD |
30000 |
C_DDR_TREFC |
70300000 |
C_DDR_TREFI |
7800000 |
C_DDR_TRFC |
100000 |
C_DDR_TRP |
30000 |
C_DDR_TRRD |
20000 |
C_DDR_TWR |
20000 |
C_DDR_TWTR |
1 |
C_ECC_BASEADDR |
0b11111111111111111111111111111111 |
C_ECC_DEC_THRESHOLD |
1 |
C_ECC_DEFAULT_ON |
1 |
C_ECC_HIGHADDR |
0b00000000000000000000000000000000 |
C_ECC_PEC_THRESHOLD |
1 |
C_ECC_SEC_THRESHOLD |
1 |
C_ENABLE_ECC_REG |
1 |
|
|
Name |
Value |
C_FAMILY |
virtex2p |
C_INCLUDE_BURST_CACHELN_SUPPORT |
1 |
C_INCLUDE_ECC_INTR |
0 |
C_INCLUDE_ECC_SUPPORT |
0 |
C_INCLUDE_ECC_TEST |
0 |
C_MEM0_BASEADDR |
0x00000000 |
C_MEM0_HIGHADDR |
0x0fffffff |
C_MEM1_BASEADDR |
0x10000000 |
C_MEM1_HIGHADDR |
0x1fffffff |
C_MEM2_BASEADDR |
0b11111111111111111111111111111111 |
C_MEM2_HIGHADDR |
0b00000000000000000000000000000000 |
C_MEM3_BASEADDR |
0b11111111111111111111111111111111 |
C_MEM3_HIGHADDR |
0b00000000000000000000000000000000 |
C_NUM_BANKS_MEM |
2 |
C_NUM_CLK_PAIRS |
4 |
C_PLB_AWIDTH |
32 |
C_PLB_CLK_PERIOD_PS |
10000 |
C_PLB_DWIDTH |
64 |
C_PLB_MID_WIDTH |
1 |
C_PLB_NUM_MASTERS |
2 |
C_REG_DIMM |
0 |
C_SIM_INIT_TIME_PS |
200000000 |
NUM_ECC_BITS |
7 |
|
|
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
1336 |
13696 |
9 |
Slice Flip Flops |
1441 |
27392 |
5 |
4 input LUTs |
1212 |
27392 |
4 |
bonded IOBs |
503 |
556 |
90 |
|
|
iocm_cntlr
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
SLAVE |
ISOCM |
ISOCM |
iocm |
ppc405_0 |
TRANSPARENT |
DCR_WRITE_PORT |
NA |
isocm_porta |
isocm_bram |
TRANSPARENT |
INSTRN_READ_PORT |
NA |
isocm_portb |
isocm_bram |
|
General |
IP Core |
isbram_if_cntlr |
Version |
3.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0xfffff000 |
C_BRAM_EN |
0 |
C_HIGHADDR |
0xffffffff |
C_RANGECHECK |
0 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
16 |
13696 |
0 |
4 input LUTs |
32 |
27392 |
0 |
bonded IOBs |
510 |
556 |
91 |
|
|
|
|
|
RS232_Uart_1
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
OPB_Clk |
I |
1 |
sys_clk_s |
2 |
RX |
I |
1 |
fpga_0_RS232_Uart_1_RX |
3 |
TX |
O |
1 |
fpga_0_RS232_Uart_1_TX |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
SLAVE |
SOPB |
OPB |
opb |
NA |
|
General |
IP Core |
opb_uartlite |
Version |
1.00.b |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0x40600000 |
C_BAUDRATE |
9600 |
C_CLK_FREQ |
100000000 |
C_DATA_BITS |
8 |
C_HIGHADDR |
0x4060ffff |
C_ODD_PARITY |
0 |
C_OPB_AWIDTH |
32 |
C_OPB_DWIDTH |
32 |
C_USE_PARITY |
0 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
54 |
13696 |
0 |
Slice Flip Flops |
64 |
27392 |
0 |
4 input LUTs |
88 |
27392 |
0 |
bonded IOBs |
112 |
556 |
20 |
|
|
|
|
accel_sort_plb_0
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
PLB_Clk |
I |
1 |
sys_clk_s |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
SLAVE |
SPLB |
PLB |
plb |
NA |
|
General |
IP Core |
accel_sort_plb |
Version |
1.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0xcc800000 |
C_FAMILY |
virtex2p |
C_HIGHADDR |
0xcc80ffff |
C_PLB_AWIDTH |
32 |
C_PLB_DWIDTH |
64 |
C_PLB_MID_WIDTH |
1 |
C_PLB_NUM_MASTERS |
2 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
4159 |
13696 |
30 |
Slice Flip Flops |
3173 |
27392 |
11 |
4 input LUTs |
7685 |
27392 |
28 |
bonded IOBs |
217 |
556 |
39 |
BRAMs |
4 |
136 |
2 |
|
|
|
|
clk90_inv
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
Op1 |
I |
1 |
clk_90_s |
2 |
Res |
O |
1 |
clk_90_n_s |
|
General |
IP Core |
util_vector_logic |
Version |
1.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_OPERATION |
not |
C_SIZE |
1 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
3 |
556 |
0 |
|
|
|
|
dcm_0
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
CLKIN |
I |
1 |
dcm_clk_s |
2 |
CLKFB |
I |
1 |
sys_clk_s |
3 |
RST |
I |
1 |
net_gnd |
4 |
CLK0 |
O |
1 |
sys_clk_s |
5 |
CLK90 |
O |
1 |
clk_90_s |
6 |
CLKFX |
O |
1 |
proc_clk_s |
7 |
LOCKED |
O |
1 |
dcm_0_lock |
|
General |
IP Core |
dcm_module |
Version |
1.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_CLK0_BUF |
TRUE |
C_CLK180_BUF |
FALSE |
C_CLK270_BUF |
FALSE |
C_CLK2X180_BUF |
FALSE |
C_CLK2X_BUF |
FALSE |
C_CLK90_BUF |
TRUE |
C_CLKDV_BUF |
FALSE |
C_CLKDV_DIVIDE |
2.0 |
C_CLKFB_BUF |
FALSE |
C_CLKFX180_BUF |
FALSE |
C_CLKFX_BUF |
TRUE |
C_CLKFX_DIVIDE |
1 |
C_CLKFX_MULTIPLY |
3 |
C_CLKIN_BUF |
FALSE |
|
|
Name |
Value |
C_CLKIN_DIVIDE_BY_2 |
FALSE |
C_CLKIN_PERIOD |
10.000000 |
C_CLKOUT_PHASE_SHIFT |
NONE |
C_CLK_FEEDBACK |
1X |
C_DESKEW_ADJUST |
SYSTEM_SYNCHRONOUS |
C_DFS_FREQUENCY_MODE |
LOW |
C_DLL_FREQUENCY_MODE |
LOW |
C_DSS_MODE |
NONE |
C_DUTY_CYCLE_CORRECTION |
TRUE |
C_EXT_RESET_HIGH |
1 |
C_FAMILY |
virtex2p |
C_PHASE_SHIFT |
0 |
C_STARTUP_WAIT |
FALSE |
|
|
|
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
26 |
556 |
4 |
GCLKs |
3 |
16 |
18 |
DCM_ADVs |
1 |
8 |
12 |
|
|
|
|
dcm_1
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
CLKIN |
I |
1 |
ddr_feedback_s |
2 |
CLKFB |
I |
1 |
dcm_1_FB |
3 |
RST |
I |
1 |
dcm_0_lock |
4 |
CLK90 |
O |
1 |
ddr_clk_90_s |
5 |
CLK0 |
O |
1 |
dcm_1_FB |
6 |
LOCKED |
O |
1 |
dcm_1_lock |
|
General |
IP Core |
dcm_module |
Version |
1.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_CLK0_BUF |
TRUE |
C_CLK180_BUF |
FALSE |
C_CLK270_BUF |
FALSE |
C_CLK2X180_BUF |
FALSE |
C_CLK2X_BUF |
FALSE |
C_CLK90_BUF |
TRUE |
C_CLKDV_BUF |
FALSE |
C_CLKDV_DIVIDE |
2.0 |
C_CLKFB_BUF |
FALSE |
C_CLKFX180_BUF |
FALSE |
C_CLKFX_BUF |
FALSE |
C_CLKFX_DIVIDE |
1 |
C_CLKFX_MULTIPLY |
4 |
C_CLKIN_BUF |
FALSE |
|
|
Name |
Value |
C_CLKIN_DIVIDE_BY_2 |
FALSE |
C_CLKIN_PERIOD |
10.000000 |
C_CLKOUT_PHASE_SHIFT |
FIXED |
C_CLK_FEEDBACK |
1X |
C_DESKEW_ADJUST |
SYSTEM_SYNCHRONOUS |
C_DFS_FREQUENCY_MODE |
LOW |
C_DLL_FREQUENCY_MODE |
LOW |
C_DSS_MODE |
NONE |
C_DUTY_CYCLE_CORRECTION |
TRUE |
C_EXT_RESET_HIGH |
0 |
C_FAMILY |
virtex2p |
C_PHASE_SHIFT |
60 |
C_STARTUP_WAIT |
FALSE |
|
|
|
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
26 |
556 |
4 |
GCLKs |
2 |
16 |
12 |
DCM_ADVs |
1 |
8 |
12 |
|
|
|
|
ddr_clk90_inv
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
Op1 |
I |
1 |
ddr_clk_90_s |
2 |
Res |
O |
1 |
ddr_clk_90_n_s |
|
General |
IP Core |
util_vector_logic |
Version |
1.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_OPERATION |
not |
C_SIZE |
1 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
3 |
556 |
0 |
|
|
|
|
jtagppc_0
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
Bus Interfaces |
TYPE |
NAME |
STD |
BUS |
P2P |
TRANSPARENT |
JTAGPPC0 |
NA |
jtagppc_0_0 |
ppc405_0 |
TRANSPARENT |
JTAGPPC1 |
NA |
jtagppc_0_1 |
ppc405_1 |
|
General |
IP Core |
jtagppc_cntlr |
Version |
2.00.a |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_DEVICE |
2vp30 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
1 |
13696 |
0 |
4 input LUTs |
1 |
27392 |
0 |
bonded IOBs |
17 |
556 |
3 |
|
|
|
|
sysclk_inv
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
Op1 |
I |
1 |
sys_clk_s |
2 |
Res |
O |
1 |
sys_clk_n_s |
|
General |
IP Core |
util_vector_logic |
Version |
1.00.a |
Driver |
API |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_OPERATION |
not |
C_SIZE |
1 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
bonded IOBs |
3 |
556 |
0 |
|
|
|
|
|
reset_block
|
 |
PINOUT |
The ports listed here are only those connected in the MHS file.
Refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[MSB:LSB] |
SIGNAL |
1 |
Ext_Reset_In |
I |
1 |
sys_rst_s |
2 |
Slowest_sync_clk |
I |
1 |
sys_clk_s |
3 |
Chip_Reset_Req |
I |
1 |
C405RSTCHIPRESETREQ |
4 |
Core_Reset_Req |
I |
1 |
C405RSTCORERESETREQ |
5 |
System_Reset_Req |
I |
1 |
C405RSTSYSRESETREQ |
6 |
Dcm_locked |
I |
1 |
dcm_1_lock |
7 |
Rstc405resetchip |
O |
1 |
RSTC405RESETCHIP |
8 |
Rstc405resetcore |
O |
1 |
RSTC405RESETCORE |
9 |
Rstc405resetsys |
O |
1 |
RSTC405RESETSYS |
10 |
Bus_Struct_Reset |
O |
1 |
sys_bus_reset |
|
General |
IP Core |
proc_sys_reset |
Version |
1.00.a |
Parameters |
These are parameters set for this module.
Refer to the IP documentation for complete information about module parameters.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_AUX_RESET_HIGH |
1 |
C_AUX_RST_WIDTH |
4 |
C_EXT_RESET_HIGH |
0 |
C_EXT_RST_WIDTH |
4 |
C_NUM_BUS_RST |
1 |
C_NUM_PERP_RST |
1 |
Post Synthesis Device Utilization |
Resource Type |
Used |
Available |
Percent |
Slices |
35 |
13696 |
0 |
Slice Flip Flops |
58 |
27392 |
0 |
4 input LUTs |
34 |
27392 |
0 |
bonded IOBs |
12 |
556 |
2 |
|
|
|
|
|