EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin O 0:2 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk 1GLB fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin O 0:2 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn 2GLB fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s 3A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin IO 0:7 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS 4A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin IO 0:63 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ 5A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin O 0:12 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr 6A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin O 0:1 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr 7A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn 8A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin O 0:1 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 9A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin O 0:1 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn 10A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin O 0:7 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM 11A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn 12A fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn 13B fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 14B fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 15C sys_clk_pin I 1 dcm_clk_s  CLK  16D fpga_0_DDR_CLK_FB I 1 ddr_feedback_s 17E sys_rst_pin I 1 sys_rst_s