# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
0GLB
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin |
O |
0:2 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk |
|
1GLB
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin |
O |
0:2 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn |
|
2GLB
|
fpga_0_DDR_CLK_FB_OUT |
O |
1 |
ddr_clk_feedback_out_s |
|
3A
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin |
IO |
0:7 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS |
|
4A
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin |
IO |
0:63 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ |
|
5A
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin |
O |
0:12 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr |
|
6A
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin |
O |
0:1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr |
|
7A
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin |
O |
1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn |
|
8A
|
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin |
O |
0:1 |
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE |
|