October 15

Chair	Time
	8:45 - 9:30	Registration
	9:15-9:30	Welcome Patricia Derler, Sicun Gao
	9:30 - 10:30	Keynote: Sanjit Seshia, University of California at Berkeley UCLID5: Integrating Modeling, Verification, Synthesis and Learning
	10:30-11:00	Break
	11:00 - 11:30	Maden Skelin and Marc Geilen, It's a Matter of Time: Modeling and Analysis of Time Dependent Systems Using Scenario-Aware Dataflow
	11:30 - 12:00	Michael Witterauf and Jürgen Teich, Run-time Requirement Enforcement for Loop Programs on Processor Arrays
	12:00-13:30	Lunch
	13:30 - 15:00	Tutorial: Jun Sun, Singapore University of Technology and Design Software Engineering Techniques for Cyber-Physical Systems
	15:00 - 15:30	Break
	15:30 - 16:00	Partha S. Roop, Hammond Pearce and Keyan Monadjem, Synchronous neural networks for cyber-physical systems
	16:00 - 16:30	Chih-Hong Cheng, Georg Nührenberg, Chung-Hao Huang, Harald Ruess and Hirotoshi Yasuoka, Towards Dependability Metrics for Neural Networks (WIP)
	16:30 - 17:00	Nagaraj S, Seshachalam D and Sunil Hucharaddi, Model Order Reduction of Nonlinear Circuit using Proper Orthogonal Decomposition and Nonlinear Autoregressive with eXogenous input (NARX) Neural Network (WIP)
	19:00	Reception

October 16

Chair	Time
	9:30 - 10:30	Keynote: Kwangheun Yi, Seoul National University Scalable Global Static Analysis, Validation, and Secrecy
	10:30-11:00	Break
	11:00 - 11:30	Srinivas Pinisetty, Partha S. Roop, Vidula Sawant and Gerardo Schneider, Security of Pacemakers using Runtime Verification
	11:30 - 12:00	Yanan Liu, Yong Guan, Xiaojuan Li, Rui Wang and Jie Zhang, Formal Analysis and Verification of DDS in ROS2
	12:00-13:30	Lunch
	13:30 - 14:30	Special Session: Keynote: Chen Gang, PLC Ladder Logic Testing and its Application in Railway Interlocking
	14:30 - 15:00	Hong Ye, AVIC Xian Aeronautics Computing Technique Research Institute Towards Safety and Determinacy in Airborne Software -- Design and Verification
	15:00 - 15:30	Haifeng Wang, National Engineering Research Centre of Rail Transportation Modeling and safety analysis of CTCS-3 train control system for high-speed railway
	15:30 - 16:00	Lei Qiao, Beijing Institute of Control Engineerin, China Academy of Space Technology Phased Hierarchical Formal Verification of Memory Management System for Spacecraft
	16:00 - 16:30	Coffee break
	16:30 - 17:00	Henguo Zhu, A Control System Modeling and Simulation Framework used in Metro ATO System
	17:00 - 17:30	Bohan Wang, Practice of Model Based System/Software Engineering in CASIC
	17:30 - 18:00	Zhibin Yang, A Practical AADL Study in Aerospace Software: from Requirement to Implementation
	19:00	Banquet

October 17

Chair	Time
	9:00 - 10:00	Keynote: Wang Yi, Uppsala University The Cause-Effect Latency Problem in Real-Time Systems with Non-Blocking Communication
	10:00-10:30	Break
	10:30 - 11:00	Ínigo Íncer Romeo, Alberto Sangiovanni-Vincentelli, Chung-Wei Lin and Eunsuk Kang, Quotient for Assume-Guarantee Contracts
	11:00 - 11:30	Jonatan Wiik, Johan Ersfolk and Marina Waldén, A Contract-Based Approach to Scheduling and Verification of Dynamic Dataflow Networks
	11:30 - 12:00	Jinmiao Xu, Zhibin Yang, Zhiqiu Huang, Yong Zhou, Chengwei Liu, Jean-Paul Bodeveix, Lei Xue and Mamoun Filali, Hierarchical Behavior Annex: Towards an AADL Functional Specification Extension
	12:00-13:30	Lunch
	13:30 - 15:00	Tutorial: Shuling Wang, Institute of Software, Chinese Academy of Science Formal Design of Cyber-Physical Systems
	15:00 - 15:30	Break
	15:30 - 16:00	Tripti Jain and Klaus Schneider, Optimal Self-Routing Split Modules for Radix-based Interconnection Networks
	16:00 - 16:30	Yu Bai, Desynchronization: From Macro-step to Micro-step
	16:30 - 16:45	Final Remarks