FMGALS'09 is the 4th edition in a series of bi-annual workshops held in Pisa in 2003 (in conjunction with FME'03), in Verona in 2005 and Nice in 2007 (in conjunction with MEMOCODE'05 and MEMOCODE'07). Past workshop proceedings have been published with Elsevier's Electronic Notes in Theoretical Computer Science (ENTCS). Special issues of the Springer Journal Formal Methods in System Design and of the IEEE Design and Test magazine have been edited including most influential contributions to the workshop.
Organizers
Sandeep K. Shukla, Virginia Polytechnic and State University, Blacksburg, USA
Jean-Pierre Talpin, INRIA Rennes-Bretagne-Atlantique, France
Keynote
David Kinniment, University of Newcastle upon Tyne, UK
Invited Lecture
Ken Stevens, University of Utah
Program
- 08:50 - Welcome
- 09:00 - Keynote
- David Kinniment, University of Newcastle upon Tyne, UK
- 10:30 - Coffer Break
- 11:00 - Technical Session - Chair TBA
- Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis - Mario R. Casu and Luca Macchiarulo
- Latency-Insensitive Design: Retry Relay-Station and Fusion Shell - Julien Boucaron, Anthony Coadou and Robert de Simone
- GALS for bursty data transfer based on the clock coupling - Milos Krstic, Xin Fan, Eckhard Grass, and Frank Gurkanyak
- 12:30 - Lunch
- 13:30 - Invited Lecture
- Ken Stevens, University of Utah, USA
- 14:30 Coffee Break
- 15:00 - Technical Session - Chair TBA
- Desynchronization techniques using Petri nets - Sohini Dasgupta and Alex Yakovlev
- An analysis of the composition of synchronous systems - Bijoy A. Jose, Bin Xue and Sandeep K. Shukla
- Modeling and Analysis of latency-insensitive Protocol Using SIGNAL Framework - Bin Xue, Sandeep K. Shukla
- 16:30 - Discussion - Chair TBA
- 17:00 - Close
Goal
To bring together formal methods experts, asynchronous system
designers and tools developers for GALS design. Identify scopes of formal
methods in GALS design.
Scope
All aspects of research on GALS architecture including, but not limited to, models of computation, formal methods, modeling frameworks and tools, formal verification techniques, design automation, experimental results and case studies
Description
Increasing cores and clock speed and decreasing engraving size of synchronous circuits raise taunting clock distribution and power leakage problems. For this reason, the Globally Asynchronous Locally Synchronous (GALS) model of computation has emerged as the paradigm of choice for SoC design with multiple timing domains, as well as for the software embedded on such circuits. Due to the inherent subtleties of asynchronous circuit design, formal methods are vital to make the GALS paradigm a success in the CAD industry. The FMGALS workshop aims at bringing together researchers from different communities interested in GALS design, and in applying formal methods in creating CAD tools enabling correct by construction GALS design.
FMGALS'09 invites papers on formal methods for GALS systems or that target
any type of architecture combining synchronous and asynchronous notions of
timing. Submissions reporting preliminary work are also encouraged. In
particular, contributions are invited on the following topics, but not limited to:
- Formal design and synthesis techniques for GALS
- GALS model of computation for software architectures
- Architectural transformations and equivalences
- Formal verification of GALS systems
- Formal methods for analysis of GALS systems
- Hardware compilation of GALS system
- Latency-insensitive synchronous systems
- Mixed synchronous-asynchronous systems
- Synchronous/asynchronous interaction
- Clocking, interconnect and interface issues
- Interfaces between multiple timing domains
- System decomposition into GALS architectures
- Formal aspects of SoC and NoC design
- Case studies, comparisons and applications
Publication
The proceedings of the workshop will be published with Elsevier's Electronic Notes in Theoretical Computer Science (ENTCS).
Submissions
Submissions shall be prepared in accordance with the ENTCS guidelines. The length of the initial submission is limited to the 15 pages in ENTCS format. Submitted manuscripts should be previously unpublished and should not have been concurrently submitted elsewhere. Submissions may be sent sent by e-mail to the workshop organizers.
Program Committee
- Luca Carloni, Columbia University
- Mario Casu, Politecnico di Torino
- Supratik Chakraborty, IIT Bombay
- Jordi Cortadella, Universitat Politecnica de Catalunya
- Marten van Hulst, Handshake Solutions
- Michael Kishinevsky, Intel
- Luciano Lavagno, Politecnico di Torino
- Steven Nowick, Columbia University
- Dumitru Potop-Butucaru, INRIA Paris-Rocquencourt
- Sandeep Shukla, Virginia Tech
- Robert de Simone, INRIA Sophia Antipolis-Mediterannee
- Ken Stevens, University of Utah
- Jean-Pierre Talpin, INRIA Rennes-Bretagne-Atlantique
- Michael Theobald, D. E. Shaw Research
- Alex Yakovlev, University of Newcastle
Timetable
January 16, 2009, submission deadlineFebruary 16, 2009, notification of acceptance- February 28, 2009, final papers due
- April 24, 2009, workshop venue
