First ACM & IEEE International Conference on

Formal Methods and Models for Codesign (MEMOCODE'2003)

Programming models, formal analysis methods and verification techniques for high-level
system design and (re)engineering: towards convergence of formal methods and industrial trends.

June 24th.-26th., 2003 -- Mont Saint-Michel, France

Home page
Aims and scope
Call for papers
Industrial case studies

I. Conformance checking
Arvind, Stan Liao, Nancy Lynch, Carl Pixley, Rob Slater, Marten Van Hulst

II. Hierarchical verification
Forrest Brewer, Hans Eveking, Grant Martin

III. Abstraction vs. optimization
Brian Bailey, Stephen Edwards, Rajesh Gupta, James Hoe

IV. Incremental verification
Harry Foster, Hillel Miller, Marten Van Hulst

V. Post-production patchability
Forrest Brewer, Masahiro Fujita

Industrial case studies. Prospective authors are invited to submit novel and unpublish work devoted to the presentation of position papers and scientific contributions on actual design problems proposed by members of the program committee from major EDA industry companies.

Problem V : Post-fabrication verification update and patch

Authors : Forrest Brewer, Masahiro Fujita

Given circuit growth in complexity and the desire to reduce time to market, it is reasonable to assume that designs may not be fully verified before tapeout. Mechanisms to allow after-fabrication modification of function, programmability or correction could be added to current designs. This is already done for large memory blocks, by adding redundant circuits and either automated or invasive reconfiguration to increase the fabrication yield.

Such updates could be made during the manufacturing process (design revision) or even after the product is in service (field upgrade). Several techniques and scenarios come to mind including eeprom or flash based firmware, FPGA logic blocks, CPLD sequencers and classical techniques such as writable uCode.

While these are very different techniques, they all trade-off implementation cost versus reconfigurable flexibility differently. Formally, verification seeks to model an implementation and determine if a set of pre-specified properties hold for the model. What is the appropriate analog if the implementations are allowed to contain sub-systems with large but bounded programmability? What properties provide for sound specification and design given this freedom?

a) What is the role of such programmability in chip designs at various levels of functional hierarchy?
b) Can a coverage metric be devised which grades the scope of changes possible by subsequent field upgrade?
c) Can families of programmable interface protocols be defined so that a wide variety of differing applications can be accommodated by a very limited number of fabricated die? (This problem is made more difficult by the requirement that such interfaces might necessarily operate at very high speeds, so the modifiable scope must be carefully controlled).
d) A common technique to introduce programmable behavior is to add a processor IP core to a system. It is still common, however, for the system design to have very limited flexibility for differing applications or to accommodate interface or computation bugs. What further types of programmability could be inexpensively added to a system to increase the flexibility?